1. Technical Field
This invention generally relates to an amplifier design. More particularly, the present invention relates to a split sense amplifier and a staging buffer suitable for use with high speed memory architectures.
2. Discussion
The application of sense amplifiers and staging buffers in highly integrated memory architectures is generally known within the electronics art. As the requirement for larger and significantly faster memory architectures increases, circuit designers are forced to produce memory chips with ever increasing numbers of transistors which form these memory locations. Furthermore, integrated memory circuits require additional transistor based circuitry to support the larger memory architectures. The performance of this supporting circuitry becomes even more important when the memory chips are switched or clocked at the increased speeds associated with high throughput microprocessors. As such, these memory architectures require larger amounts of power, which in turn creates additional problems for integrated circuit designers. Examples of these problems are increased noise propagation and higher capacitive loading placed upon the data bus channels.
To overcome the problems with the capacitive loads associated with the data bus channels, sense amplifiers were incorporated within the integrated memory circuit to drive the digital logic voltage signals between the two logic states, typically between 0 volts and 5.0 volts. The sense amplifier was designed to determine the logic state of a particular low voltage data signal stored in memory by comparing the voltage levels of the data signal against preset threshold parameters, and then driving the particular data signal to the appropriate 0 volt or 5.0 volt signal level, also referred to as the full swing voltage level. However, the technique of transferring the data signals from memory to other circuits at the full swing voltage level provided by the sense amplifiers required additional power. This power was not always available, or if available, created excess heat which had to be dissipated from the chip. One way of reducing power was to reduce the voltage swing level from 5.0 volts to 3.3 volts. However, the power reduction achieved by this change was soon lost through the addition of more transistors.
Additionally, as the demand for more complex signal processors increases, so does the demand for wider memory architectures. For example, FFT processors and vector processors are typically based upon highly parallel computer architectures. This means that the conventional 32 and 64 bit data bus channels associated with current high performance microprocessors will be replaced with a data bus including from 500 to 4,000 data channels. This increase in the number of data channels, or strip transmission lines formed on the silicon chip, also significantly increases the total load placed on the circuit.
To assist these highly parallel processors in operating more efficiently, staging buffers were added to the memory architectures supporting these processors. While the addition of staging buffers achieved the goal of increasing processor throughput and efficiency, the staging buffers coupled to the sense amplifiers will potentially increase the loading placed upon the memory circuit, and accordingly increase the total power consumed by the memory circuit. Thus, it is desirable to provide a high density memory architecture which can implement staging buffers integrated within a conventional sense amplifier for reducing the power consumed by the memory circuit. Such a reduction could be achieved by transferring the data signal from the sense amplifier to the staging buffer at voltage levels significantly lower than the typical full swing voltage level. This technique would serve to significantly reduce the amount of power consumed by the memory circuit and accordingly allows more transistors to be integrated into a single integrated circuit package.
The conventional approach to designing the interface between a wide memory architecture and its high speed staging buffers is to have a separate multi-stage sense amplifier provide a full swing voltage signal onto the data bus, and transfer the full swing voltage signal across the data bus to the staging buffers which act as a register to store these data values. Since the wide memory architecture associated with parallel processors requires a large number of data bus channels, and therefore staging buffers (typically between 500 and 4,000), and because the capacitive loading of each of these channels is relatively high, the switching power of these data bus channels becomes a significant portion of the total power consumed by the memory circuit. This level of power consumption only increases when the switching frequency of the memory circuit is increased. Accordingly, it is desirable to provide a sense amplifier and staging buffer design which is capable of reducing this power by at least one order of magnitude without paying a significant penalty in performance or heat and noise generation.